IJSRD - International Journal for Scientific Research & Development| Vol.

4, Issue 03, 2016 | ISSN (online): 2321-0613

An Efficient Error Correction Code for A Smart Reliable Network-on-
P.G Scholar 2Assistant Professor
Department of Electronics and Communication Engineering
Bangalore Institute of Technology, Bangalore, India
Abstract— Networks on Chip plays a vital role in destination through the routers is defined by the routing
development of VLSI design and it is one of the solutions for algorithm. Therefore, the path that a data packet is allowed to
faster on chip communication. In this paper a new network- take in the network depends mainly on the adaptiveness
on-chip is proposed that handles accurate localizations of the permitted by the routing algorithm, which is applied locally
faulty parts of the NoC. The proposed NoC handles new error in each router being crossed and to each data packet.
detection mechanisms suitable for dynamic NoCs, and the The partial dynamic reconfiguration of FPGAs with
errors are detected and corrected efficiently in order to have varying position and the number of implemented PEs and IPs,
a fault free data transmission. The presented mechanisms are higher adaptiveness is allowed in MPSoCs during runtime.
able to distinguish permanent and transient errors and localize Hence dynamically reconfigurable 2-D mesh NoCs (DyNoC,
accurately the position of the faulty blocks such as data bus, CuNoC, QNoC, ConoChi, etc.) are suitable for field
input port, output port in the NoC routers, while preserving programmable gate array (FPGA)-based systems. To achieve
the throughput, the network load, and the data packet latency. a reconfigurable NoC, an efficient dynamic routing algorithm
The proposed method uses Decimal Matrix Code concept is required for the data packets. The goal is to preserve
which utilizes decimal algorithm to obtain the maximum flexibility and reliability while providing high NoC
error detection capability. The proposed DMC is compared to performance in terms of throughput.
the existing Hamming code which corrects only one bit error, Fig. 1(a) depicts the communication between
whereas DMC can correct up to 16 bits error. As a result this different processor elements (PE’s) of a dynamic reliable
improves the error correction capability and enhances data NoC. Fig 1(b) and Fig 1(c) depicts the placement of PE’s
reliability. dynamically and the occurrence of nodes with faults. In both
Key words: Network-On-Chip (NoC), Decimal Matrix Code the cases the bypass through the routers is determined by the
(DCM), Dynamic NoCs dynamic routing algorithm. Fig 1(c) shows regions with
faulty nodes which make the communication impossible with
I. INTRODUCTION routing algorithms that are not adaptive. This shows the need
The intricacy of each component in a system increases for algorithms that are fault tolerant and highly adaptive that
rapidly as the volume and density of VLSI design increases. can be used dynamic NoCs during runtime.
In order to meet the requirements of real-time applications the MPSoCs are becoming more sensitive to
trend of embedded systems has been moving toward phenomena that generate permanent, transient, or intermittent
multiprocessor systems-on-chip (MPSoCs). The traditional faults [10] because of the increasing complexity and the
bus-based communication methods are not able to keep up reliability evolution of SoCs. These faults may generate data
with the increasing requirements of future SoCs in terms of packet errors, or may affect router behavior leading to data
performance, timing closure, power, scalability etc. The packet losses or permanent routing errors. Indeed, a fault in a
complexity of these SoCs is increasing and the routing logic will often lead to packet routing errors and
communication medium is becoming a major issue of the might even crash the router. To detect these errors, specific
MPSoC [6]. To satisfy the design productivity and signal error detection blocks are required in the network to locate
integrity challenges of next-generation system designs, a the faulty sources. Indeed, the precise location of permanent
structured and scalable interconnection architecture, Network faulty parts of the NoC must be determined, in order for them
on-Chip, has been proposed recently to reduce the complex to be bypassed effectively by the adaptive routing algorithm.
on-chip communication problem. The integration of a For handling message routing errors in dynamic networks, a
network-on-chip (NoC) into the SoC gives an effective means new faulty switch detection mechanism is required for
to interconnect several processor elements (PEs) or adaptive or fault-tolerant routing algorithms. The error
intellectual properties (IP) (processors, memory controllers, correction codes (ECCs) are implemented inside the NOC
etc.). Although NoCs can adopt concepts and methods from components in order to protect data packets against errors.
the well-established platforms of computer networking, it is
impractical to blindly reuse features of existing computer
networks and symmetric multiprocessors. In particular, NoC
switches should be energy-efficient, small and fast. For early
NoC research neglecting these views along with proper
comparison was typical but nowadays they are considered in
more detail. The NoC medium features a high level of
modularity, flexibility, and throughput. An NoC comprises
Fig. 1: Illustration Of A Dynamic Reliable Noc. (A) Normal
routers and interconnections allowing communication
Operation. (B)Dynamic Implementation Of An IP. (C)
between the PEs and/or IPs. The NoC relies on data packet
Online Detection Of A Faulty Router.
exchange. The path for a data packet between a source and a

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An Efficient Error Correction Code for A Smart Reliable Network-on-Chip
(IJSRD/Vol. 4/Issue 03/2016/336)

In this paper, a novel decimal matrix code (DMC)
[2] based on divide-symbol is proposed to provide enhanced
memory reliability. The proposed DMC utilizes decimal
algorithm which involves decimal integer addition and
decimal integer subtraction to detect and correct errors. The
advantage of using decimal algorithm is that the error
detection capability is maximized so that the reliability of
memory is enhanced.
This paper is divided into the following sections.
The existing system is presented in Section II. Section III
illustrates the proposed system and the decimal matrix code
concept. In Section IV the simulation results are illustrated
and Section V gives the conclusion of the paper.

The architecture of RKT-NoC switch [1] is as shown in the
Fig 2. The RKT-NoC is a packet- switched network based on
intelligent independent reliable routers called RKT-switches.
The switch has four directions i.e., North, South, East, and
West which is needed for a 2-D mesh NoC. The IPs and PEs
can be linked directly to any side of the router and thus there
is no need of specific connection. This proposed mechanism Fig. 2: Architecture of Reliable Router RKT Switch
can be applicable to NoCs using five port routers with a local The Hamming ECC is considered for our RKT-
port dedicated to an IP but when this local port has permanent switch, in order to provide a convenient tradeoff between area
error the IP connected to this port is permanently lost or it overhead and error correction capacity. This choice permits
needs to be moved in the chip dynamically. Hence this is the the correction of single event upset (SEU) errors (one bit flip
major drawback of using five port routers. On the other side, in a flit) and the detection of multiple event upset (MEU)
that is by using four port RKT-NoC the IP can be replaced by errors (two bit flips in a flit). Moreover, the Hamming code is
several routers by having several input ports. Therefore there more suitable for NoCs based on Ack/Nack flow control than
are strongly connected in the network. The switch has two the parity bit check. Indeed, on a single bit-flip error
unidirectional data buses (input and output ports). Each input occurrence, error correction is possible with the Hamming
port has first-input, first-output (FIFO) and a routing logic ECC, whereas the single parity check would require packet
block. The switching strategy used is the store-and-forward retransmission and hence an increased transmission latency.
switching technique which is suitable for dynamically
reconfigurable NoC. This is because at any instant with the III. PROPOSED DMC METHOD
store- and-forward technique, each data packet is stored only In the proposed system we use Decimal Matrix Code to
in a single router. Hence, when a router needs to be maximize the error detection and correction capability.
reconfigured, the router is only required to empty its buffers. Decimal Matrix Codes (DMC) are mainly used to avoid soft
The automatic repeat request is the type of error errors due to multiple cell upsets in memory unit. DMC make
control method used here is which uses error detecting codes. use of decimal algorithm that is decimal integer addition and
The Ack/Nack solution is used in the existing architecture decimal integer subtraction to detect errors. In this the
which handles fault-tolerant transmissions effectively. The information bits are provided to the DMC encoder during the
packet is saved locally for packet retransmission until an Ack encoding process. As a result, the horizontal redundant bits,
or Nack is received. Once a flit with an error fails to be vertical redundant bits and the information bits are obtained.
corrected by ECC is found by the neighbouring router, a Nack Once encoding process gets completed, this codeword is
is sent back and the whole packet is retransmitted., an Ack is stored to the memory. If multiple cell upset occurs in
sent by receiver signifying that full packet is being received memory, this can be corrected during the decoding process.
correctly as a data frame as a result latency is reduced. Thus the error detection and correction capability is
Otherwise maximized due to the usage of decimal matrix code.

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An Efficient Error Correction Code for A Smart Reliable Network-on-Chip
(IJSRD/Vol. 4/Issue 03/2016/336)

Fig. 3: Proposed System symbol 0 where no errors occur. When ΔH4H3H2H1H0 and
The existing system used hamming code concept for S3 −S0 are nonzero, the induced errors are detected and
error detection and correction which corrects one bit error and located in symbol 0, and then these errors can be corrected by
detects maximum of two bit error, whereas the proposed D0correct = D0 ⊕S0. (7)
Decimal Matrix Code detects and corrects up to 16 bits of Finally, these errors can be corrected by inverting
data. This increases the data reliability and enhances the fault the values of error bits. The Fig 5 shows the flow chart of the
free data transmission between different directions of the proposed DMC method.
NoC router. The proposed system is as shown in the Fig 3,
where the DMC concept is implemented as shown.
In the proposed DMC [2], we first divide-symbol
and arrange them in matrix form i.e., the N-bit word is
divided into k symbols of m bits (N = k × m), and these
symbols are arranged in a k1 ×k2 2-D matrix. By performing
decimal integer addition of selected symbols per row the
horizontal redundant bits H are produced and thee vertical
redundant bits V are obtained by binary operation among the
bits per column. These operations are implemented in logical
instead of in physical. Hence, the proposed DMC does not
require changing the physical structure of the memory.The
Fig 4 illustrates an example to understand the proposed DMC
scheme. Here we take a 32 bit word i.e. D0 to D31 which are
the information bits. We then divide the informaton bits into
eight symbols of 4-bit. The horizontal check bits are H0–H19
and V0 through V15 are vertical check bits. The k and m
should be carefully adjusted to maximize the correction
capability and minimize the number of redundant bits.

Fig. 5: Algorithm of DMC

Fig. 4: 32-bits DMC logical organization (k = 2 × 4and m = Simulation was done in ModelSim and synthesis report was
4). summarized in Xilinx ISE 13.2. The Fig 6 below shows the
The horizontal redundant bits H can be obtained by simulation of the DMC concept used in the ECC block of the
decimal integer addition as follows: NoC router. The simulation result of the NoC router as top
H4H3H2H1H0 = D3D2D1D0 + D11D10D9D8 (1) module is shown in Fig 7.
H9H8H7H6H5 = D7D6D5D4 +D15D14D13D12 (2)
and similarly the rest of the horizontal redundant bits
are obtained where “+” represents decimal integer addition.
For the vertical redundant bits V, we have
V0 = D0 ⊕ D16 (3)
V1 = D1 ⊕ D17 (4)
and similarly for the rest vertical redundant bits.
The decoding process is required to obtain a word
being corrected. For example, first, the received redundant
bits H4H3H2H1H0΄ and V0΄−V3΄ are generated by the
received information bits D΄. Second, the horizontal
syndrome bits ΔH4H3H2H1H0 and the vertical syndrome
bits S3 −S0 can be calculated as follows:
ΔH4H3H2H1H0= H4H3H2H1H0΄ − H4H3H2H1H0 (5)
S0 = V 0 ΄ ⊕ V 0 (6)
and similarly for the rest vertical syndrome bits,
where “−” represents decimal integer subtraction.
When ΔH4H3H2H1H0 and S3 −S0 are equal to
Fig. 6: Snapshot of DMC used in ECC
zero, the stored codeword has original information bits in

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An Efficient Error Correction Code for A Smart Reliable Network-on-Chip
(IJSRD/Vol. 4/Issue 03/2016/336)

[7] C. Grecu, A. Ivanov, R. Saleh, E. Sogomonyan, and P.
Pande, “On-line fault detection and location for NoC
interconnects,” in Proc. 12th IEEE Int. On-Line Test.
Symp., Jul. 2006, pp. 145–150.
[8] J. Han, “Toward hardware-redundant, fault-tolerant
logic for nanoelectronics,” IEEE Design Test Comput.,
vol. 22, no. 4, pp. 328–339, Jul.– Aug. 2005.
[9] M. Majer, C. Bobda, A. Ahmadinia, and J. Teich,
“Packet routing in dynamically changing networks on
chip,” in Proc. 19th IEEE Int. Parallel Distrib. Process.
Symp., Apr. 2005, p. 154b.
[10] J. Wu, “A fault-tolerant and deadlock-free routing
protocol in 2d meshes based on odd-even turn model,”
IEEE Trans. Comput., vol. 52, no. 9, pp. 1154–1169,
Sep. 2003.

Fig. 7: Snapshot of NoC router operation

In this paper, we proposed new error detection mechanisms
for dynamic NoCs. The proposed routing error detection
mechanisms allows the accurate localization of permanent
faulty routing blocks in the network. The proposed DMC
method , corrects up to 16 bit error and can detect more than
16 bit error. It increases the error correction rate up to 10
times more than the existing method. Thus the error detection
and correction capability is maximized due to the usage of
decimal matrix code.

[1] Cédric Killian, Camel Tanougast, Fabrice Monteiro, and
Abbas Dandache " A Smart Reliable Network-on-Chip",
[2] Jing Guo, Liyi Xiao, Zhigang Mao, and Qiang Zhao
"Enhanced Memory Reliability Against Multiple Cell
Upsets Using Decimal Matrix Code", IEEE Transaction
on Very Large Scale integration (VLSI) Systems 2013.
[3] S. Liu, P. Reviriego, and J. A. Maestro, “Efficient
majority logic fault detection with difference-set codes
for memory applications,” IEEE Trans. Very Large Scale
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[4] M. Hosseinabady, M. Kakoee, J. Mathew, and D.
Pradhan, “Low latency and energy efficient scalable
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[5] A. Ejlali, B. Al-Hashimi, P. Rosinger, S. Miremadi, and
L. Benini, “Performability/energy tradeoff in error-
control schemes for on-chip networks,” IEEE Trans.
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1–14, Jan. 2010.
[6] K. Sekar, K. Lahiri, A. Raghunathan, and S. Dey,
“Dynamically Configurable bus topologies for high-
performance on-chip communication,” IEEE Trans.
Very Large Scale Integr. (VLSI) Syst., vol. 16, no. 10,
pp. 1413–1426, Oct. 2008.

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